Frame jitter occurs when the delay between a trigger and the start of a signal acquisition or signal generation is different among subsequence data frames. Test bench waveform signal generators features low frame jitter (e.g. 400 ps rms), but this performance is still insufficient for the instrument to be used in sensitive applications like Doppler velocimetry. In this work a circuit is presented that synchronizes on-the-fly an internal clock to every occurrence of an external trigger. It is implemented in a Field Programmable Gate Array (FPGA) and features a frame jitter lower than 100 ps rms.
FPGA-based Clock Phase Alignment Circuit for Frame Jitter Reduction / Dario Russo , Stefano Ricci. - STAMPA. - 627:(2020), pp. 199-205. (Intervento presentato al convegno International Conference on Applications in Electronics Pervading Industry, Environment and Society, ApplePies 2019 tenutosi a Pisa nel 11-13 Settembre 2019) [10.1007/978-3-030-37277-4_23].
FPGA-based Clock Phase Alignment Circuit for Frame Jitter Reduction
Dario Russo;Stefano Ricci
2020
Abstract
Frame jitter occurs when the delay between a trigger and the start of a signal acquisition or signal generation is different among subsequence data frames. Test bench waveform signal generators features low frame jitter (e.g. 400 ps rms), but this performance is still insufficient for the instrument to be used in sensitive applications like Doppler velocimetry. In this work a circuit is presented that synchronizes on-the-fly an internal clock to every occurrence of an external trigger. It is implemented in a Field Programmable Gate Array (FPGA) and features a frame jitter lower than 100 ps rms.
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