FPGA Implementation of a Synchronization Circuit for Arbitrary Trigger Sequences

In several applications the generation/acquisition of data sequences is triggered by an external signal. Frame jitter, i.e. random temporal variations between the trigger signal and the actual start of data generation/acquisition, produces errors and inaccuracies. When, in a digital approach, the trigger is sampled by the internal clock of the receiving system, an uncertainty corresponding to the clock period (e.g. 10 ns for a 100 MHz clock) is produced. For several sensitive applications, like, for example, radar interferometry or ultrasound velocimetry, this uncertainty cannot be tolerated, making difficult the synchronization of external instrumentation or separated apparatuses. The problem is theoretically solved by sharing a common master clock among instruments, but not all the systems allow this solution. In this paper a full digital synchronization circuit is proposed that measures the phase difference between the input trigger and the next edge of its internal clock, and generates a copy of the clock with a phase tuned on the input trigger. This way, for every trigger pulse, the clock is re-phased and the frame jitter is reduced. The circuit accepts non-periodic triggers, making it suitable for a wider range of applications. Experiments with the proposed circuit implemented in a Field Programmable Gate Array (FPGA) are presented that show a frame jitter reduction below 90 ps rms.