FPGA-based Trigger-Synchronizer for low Frame-Jitter Signal Generation

Commercial waveform function generators can be set to produce signal bursts that start when a trigger pulse is applied. Unfortunately, the delay between trigger pulse and the effective burst generation is not constant, but it is affected by a jitter in the order of some hundreds of ps or more. In sensitive applications, like ultrasound Doppler, this jitter affects negatively the measurements, limiting the use of the generators in the experiments. In this paper, an FPGA re-synchronization circuit is presented that is able to re-phase an internal clock to the edge of a trigger pulse. Unlike other commercial re-synchronization devices, the trigger can be an arbitrary pulse sequence, not necessarily a clock. The circuit measures the phase between the trigger edge and its internal clock by the means of a Tapped Delay Line, and re-phase accordingly a second internal clock. Experiments show that when the proposed circuit is used for generating signal bursts triggered by an external signal, the frame jitter is below 100 ps rms.