An efficient architecture for floating point based MISO neural neworks on FPGA

The present paper documents the research towards the development of an efficient algorithm to compute the result from a multiple-input-single-output Neural Network using floating-point arithmetic on FPGA. The proposed algorithm focus on optimizing pipeline delays by splitting the "Multiply and accumulate" algorithm into separate steps using partial products. It is a revisit of the classical algorithm for NN computation, able to overcome the main computation bottleneck in FPGA environment. The proposed algorithm can be implemented into an architecture that fully exploits the pipeline performance of the floating-point arithmetic blocks, thus allowing a very fast computation for the neural network. The performance of the proposed architecture is presented using as target a Cyclone II FPGA Device.