Assessing Coverage of SW-Based Error Detection of Hardware Components According to Transition Path Delay Fault Model

Improvements in transistor technologies lead to the possibility of producing hardware (HW) systems with reduced size, lower power consumption, and higher clock frequency. Such devices are increasingly adopted in safety-critical systems, where fault detection during operation is mandatory. In those cases where the adopted safety levels do not require hardware redundancy, Software-Based Self-Test (SBST) techniques represent an effective solution, whereby diagnostic coverage must be accurately assessed through fault injection experiments. These experiments need to be done considering appropriate fault models and accounting for the effect of aging processes. To this extent, traditional fault models, such as the stuck-at fault model, are not able to capture circuit behaviour under aging-induced degradations, while the higher fidelity Transition Path Delay Fault (TPDF) model poses significant challenges in terms of complexity and tool support. In this work, we propose a complete, modular, and extensible, end-to-end methodology for coverage assessment of software-based error detection mechanisms grounded in the TPDF fault model. The methodology accounts for aging-aware selection of failing paths, fault injection within state-of-the-art Electronic Design Automation (EDA) tools, and systematic diagnostic coverage estimation considering the high variability caused by environmental and workload conditions. By bridging transistor-level aging effects and system-level coverage evaluation, the proposed methodology enables a more realistic and practical assessment of SBST effectiveness compared to existing approaches based on delay fault models.