This paper presents a new digital architecture designed to acquire and process in parallel large bandwidth signals or bidimensional data. Originally the architecture operates as attached processors to an apparatus based on general CPUs and standard buses (VXI) in an experiment of high energy physics but it's interesting also for general applications.

A hierarchical structure for real time parallel processing / G., Castellini; Pierucci, Laura; DEL RE, Enrico; A., Fort. - ELETTRONICO. - (1990), pp. 1407-1410. ((Intervento presentato al convegno EUSIPCO 1990 tenutosi a Barcellona.

A hierarchical structure for real time parallel processing

PIERUCCI, LAURA;DEL RE, ENRICO;
1990

Abstract

This paper presents a new digital architecture designed to acquire and process in parallel large bandwidth signals or bidimensional data. Originally the architecture operates as attached processors to an apparatus based on general CPUs and standard buses (VXI) in an experiment of high energy physics but it's interesting also for general applications.
Proceedings of EUSIPCO 90, 5. European Signal Processing Conference, Volume 1 Volume 1;Volume 5 di Signal processing Editore Elsevier, 1990 Lunghezza 774 pagine Esporta citazione BiBTeX EndNote RefMan
EUSIPCO 1990
Barcellona
G. Castellini; L. Pierucci; E. Del Re; A.Fort
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/2158/385604
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