This paper presents a novel 3D packaging technique for integrating large 2-D Piezoelectric Micromachined Ultrasonic Transducer (PMUT) arrays with front-end circuits using a hybrid approach. This method allows the separate fabrication of the MEMS and ASICs, offering increased design flexibility and improved production yield. The packaging process involves flip-chip bonding of a 2-D PMUT array to a Fan-Out Wafer-Level Package (FOWLP) containing front-end ASICs. A 64×64 PMUT array, operating at 2 MHz with 80% two-way bandwidth, was fabricated and connected to a FOWLP housing 4 dummy ASICs. These ASICs were designed to form a 64×4-element 1.5-D array by electrically connecting, in the elevation direction, two symmetric groups of 8 adjacent PMUT array elements. The resulting electro-acoustic module (EAM) was mounted on a rigid-flex PCB and integrated in a probe head. Electrical impedance and acoustic tests confirmed the reliability and repeatability of the 3D packaging technique.
Advanced 3-D Packaging for Integrated 2-D PMUT Arrays and Front-End Circuits / Savoia, Alessandro S.; La Mura, Monica; Dehghan Pir, Mohammad Mahdi; Boni, Enrico; Ramalli, Alessandro; Tortoli, Piero; Dutta, Rahul; Rao, Vempati Srinivasa; Soon, David Ho; Prelini, Carlo Luigi; Shaw, Mark; Giusti, Domenico. - ELETTRONICO. - (2024), pp. 1-4. (Intervento presentato al convegno 2024 IEEE Ultrasonics, Ferroelectrics, and Frequency Control Joint Symposium (UFFC-JS)) [10.1109/uffc-js60046.2024.10793875].
Advanced 3-D Packaging for Integrated 2-D PMUT Arrays and Front-End Circuits
Savoia, Alessandro S.;Boni, Enrico;Ramalli, Alessandro;Tortoli, Piero;Giusti, Domenico
2024
Abstract
This paper presents a novel 3D packaging technique for integrating large 2-D Piezoelectric Micromachined Ultrasonic Transducer (PMUT) arrays with front-end circuits using a hybrid approach. This method allows the separate fabrication of the MEMS and ASICs, offering increased design flexibility and improved production yield. The packaging process involves flip-chip bonding of a 2-D PMUT array to a Fan-Out Wafer-Level Package (FOWLP) containing front-end ASICs. A 64×64 PMUT array, operating at 2 MHz with 80% two-way bandwidth, was fabricated and connected to a FOWLP housing 4 dummy ASICs. These ASICs were designed to form a 64×4-element 1.5-D array by electrically connecting, in the elevation direction, two symmetric groups of 8 adjacent PMUT array elements. The resulting electro-acoustic module (EAM) was mounted on a rigid-flex PCB and integrated in a probe head. Electrical impedance and acoustic tests confirmed the reliability and repeatability of the 3D packaging technique.I documenti in FLORE sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.